(1) Field of the Invention
The present invention relates to a MOS image sensor comprising a dynamic shift register, in particular, to the improvement of the reset function.
(2) Description of the Related Art
Recently, an image sensor using an amplifier MOS sensor has been brought to attention. This image sensor characterized by its high sensitivity amplifies a signal detected by a photodiode for each cell indicating a pixel, using a transistor.
A dynamic shift register is used as a circuit to scan horizontally or vertically a sensor unit which has pixels arranged two-dimensionally in such image sensor as described above so as to enhance simplification, high integration and low power consumption of the circuit.
FIG. 1 is a block diagram showing a structure of the conventional image sensor. This image sensor is made up of an imaging unit 61, shift registers 62 and 63, a signal processing unit 64, and a preamp 65. The imaging unit 61 contains pixels which are arranged two-dimensionally. The shift register 62 outputs a row selection signal to select one of the rows from the imaging unit 61. The shift register 63 outputs a pixel selection signal to select a pixel in the selected row. The signal processing unit 64 derives a pixel signal from the selected pixel. The preamp 65 amplifies the derived pixel signal.
FIG. 2 is a block diagram showing a structure of the conventional NMOS dynamic-typed shift register and is utilized as the shift registers 62 and 63. The diagram only shows 4 stages; however, in actuality, there are from hundreds to thousands stages.
The clock signals Clk1 and Clk2 are two-phase clock signals, on which shifting operation bases. The clock signal Clk1 is inputted into the “2N+1”th(where N is an integer) units, and the clock signal Clk2 is inputted into the “2N”th register units. Thus, the “2N+1”th register units and the “2N”th register units operate in alternate shifts.
In FIG. 2 Res1, Res2 . . . (in a case of mentioning anyone, the abbreviation Res is used) are unit registers. These unit registers memorize a logical value of an input signal In inside in synchronization with a clock signal Clk. Then, each of the unit registers outputs the memorized logical value as the output signals, Out and Next. The output signal Out is outputted as a row selection signal or a column selection signal to the imaging unit 61.
Transistors Tr3-1,3-2, . . . (in a case of mentioning anyone, the abbreviation Tr3 is used) are reset transistors, each resetting an input signal In that is inputted to each of the unit registers. Here, the reset of the input signals means changing the level of the input signals to low level, and thus, discharges the capacity which is connected to the corresponding input signal line (e.g. the gate capacity of the transistor). In other words, each of the transistors Tr3 resets the input signal In by the following two steps. First, the Tr3 changes the level of the input signal In to low level when the output signal Out of the unit register is at high level, said unit register being next to the unit register containing the input signal In that is connected to the current transistor. Then, the Tr3 discharges the charge stored in the memory elements within both the current and the front unit registers. This is to prevent the unit register from keeping the charge forever and remaining at high-level without resetting. After resetting, the level of the input signal In falls to low-level or the state of the input signal In changes to high impedance.
Transistors Tr7-1, 7-2 . . . (in a case of mentioning anyone, the abbreviation Tr7 is used) are on when the reset control signal RS rises to high level, and reset all of the input signals of all the unit registers at once. The reset control signal RS inputs the input signal In1 of the unit register Res1 as a reset pulse right before the start pulse, in synchronization with the start pulse. Thus, all the unit registers get reset (all clear) before the start pulse is applied.
FIG. 3A is a circuit diagram showing a structure of the unit register Res. As the diagram shows, the unit register is made up of NMOS transistors Tr1, Tr2, and a capacitor C1. FIG. 3B shows an operation performed by the unit register in a case the input signal In is at high level. Because the input signal In is at high level, a gate electrode of the transistor Tr1 is already at high level due to a gate capacitor of the transistor Tr1 and a potential of the capacitor C1, before the rising edge of the clock signal Clk(in FIG. 3). In this state, when the clock signal Clk rises from low level to high level, a gate voltage In of the transistor Tr1 is boosted via the capacitor C1(in FIG. 3). Also, the potential under the gate becomes higher than the high level of the clock signal Clk since a voltage higher than the clock signal is applied to the gate of the transistor Tr1, and thereby, the Out signal is outputted at the level as high as that of the clock signal Clk(in FIG. 3). When the clock signal Clk falls to low level, the Out signal is outputted at the level as low as that of the clock signal Clk. Here, the Next signal is outputted at high level even after the fall of the clock signal Clk since the high level is held in the gate capacitor of the unidirectional transistor Tr2.
In the case the input signal In is at low level (or floating), the boost transistor Tr1 is not on, therefore, both of the Out signal and the Next signal are held at low level(or floating) even if the clock signal Clk is inputted.
FIG. 4 is a time chart showing a reset operation of the transistor Tr3 shown in FIG. 2. As shown in FIG. 4, the clock signals Clk1, Clk2, the input signals (or the internal data) In1˜In4, the output signals Out1˜Out4 are the signals shown in FIG. 2 and FIG. 3.
First, the unit register Res1 synchronizes with the Clk1 signal (in FIG. 4), and boosts the input signal In1 which is at high level to hold it inside (in FIG. 4). At the same time the unit register Res1 outputs the output signal Out1 as the pixel selection signal (in FIG. 4), and raises the level of the Next1 signal to high level. The Next 1 that has been boosted to high level is inputted as the input signal In2 into the next unit register Res2. Here, each of the other “2N+1”th unit registers where the Clk1 signal has been inputted is in the state of low level (or in the state of high impedance), and does not take in a high level signal.
In this manner, each of the “2N+1”th unit registers to which the clock signal Clk1 is provided performs a shifting operation. The next clock signal Clk2 performs a shifting operation of each of the “2N”th unit registers.
Also, when the output signal Out2 rises to high level, the reset transistor Tr3-1 is on. This Tr3-1 changes the level of the input signal In1 to low level. Then, the gate electrode of the transistor Tr1 and the charge of the capacitor C1 are discharged, which resets the input signal In1 in the unit register Res1.
When the output signal Out3 rises to high level, the reset transistor Tr3-2 is on. This causes the gate electrode of the transistor Tr1 and the capacitor C1 within the unit register Res2 to discharge. At the same time, the charge of the gate electrode of the unidirectional transistor Tr2 within the unit register Res1 is discharged via the Next1 signal line. In this respect the input signal In 2 is reset in the unit register Res2.
As mentioned above, in the NMOS dynamic shift register, the unit register which outputs the high level signal resets the input signal In which is inputted to the unit register of the front stage.
Such shift register is introduced in the Japanese Laid-Open Patent publication No. S64-44178 which discloses the advanced technology mentioned above. The Japanese Laid-Open Patent publication No. S64-44178 discloses the bidirectional shift register which can choose a shifting direction with two types of groups of transistors. One group of transistors connect the unit registers in the forward direction, and the other group of transistors connect them in the reverse direction.
FIG. 5 is a block diagram showing a structure of the conventional bidirectional shift register. There are two differences between FIG. 5 and FIG. 1. One is that the extra transistors are added: the transistors Tr4-1, Tr4-2, . . . (abbreviated as Tr4 in a case of mentioning anyone), the transistors Tr5-1. Tr5-2, . . . (Tr5), the transistors Tr8-1, Tr8-2, . . . (Tr8), the transistors Tr9-1, Tr9-2, . . . (Tr9), and the transistors Tr10-1, Tr10-2, . . . (Tr10). The other difference is that the control signals Norm and Rev are specified. These different features will be mainly explained in the following.
The control signals Norm, Rev are the signals which designate a shifting direction. In the case of (Norm, Rev)=(High Level, Low Level), they designate the forward shifting operation. In the case of (Norm, Rev)=(Low Level, High Level), they designate the backward shifting operation.
The transistor Tr4 is on when the control signal Norm is at high level, and connects the input and output of the unit register in the forward direction. Also, the transistor Tr10 is on when the control signal Norm is at high level, and transmits the output of the unit register to the reset transistor Tr3.
The transistor Tr5 is on when the control signal Rev is at high level, and connects the input and output of the unit register in the backward direction. Also, the transistor Tr9 is on when the control signal Rev is at high level, and transmits the output of the unit register to the reset transistor tr8.
In the forward shifting operation, the transistors Tr4 and Tr10 are on, and Tr5 and Tr9 are off. In this state, the unit register which outputs the high-level output signals turns on the transistor Tr3 which is connected to the input signal in the previous (the backward in the shifting direction) unit register through the transistor Tr10. In this manner, the input signal of the previous unit register is reset.
In the backward shifting operation, the transistors Tr5 and Tr9 are on, and the Tr4 and Tr10 are off. In this state, the unit register which outputs the high-level output signal turns on the transistor Tr8 which is connected to the input signal of the previous (the backward of the shifting direction) unit register through the transistor Tr9. In this manner, the input signal of the previous unit register is reset.
The transistor Tr7 is the transistor for the all-clear purpose as shown in FIG. 2, and is turned on by the reset control signal RS right before the start pulse in synchronization with the start pulse. In addition, the Japanese Laid-Open Patent publication No. H 6-104292 discloses the shift register which initiates the start at some midpoint of the shift register in order to deal with a zoom mode and the like. For example, this shift register enables scanning from the one-fourth point to the three-fourths point in the shift register.